On Mon, 2007-07-30 at 23:37 +0530, Siddhesh Poyarekar wrote:
Firstly, good example.
True, the implementation is processor-specific. But AFAIK almost all
processors in the market today implement instruction pipelining.
Differences lie in the number of instructions pre-fetched and the
branch prediction technique (anything else that impacts this
example?). Branch prediction does not figure here since the
while(true) becomes an unconditional jump. The actual number of
instructions pre-fetched only tell us about the degree to which the
impact occurs in case of a miss; I'm not concerned about the degree,
I'm only concerned about whether it does make an impact.
Well its a tough question. Well, IIRC my SP classes then there will be
an impact. But most modern processors minimize it by having multiple
multi-stage pipelines. The processor rarely runs out of code to execute.
When a miss occurs it is definitely going to dump that pipeline and
while it is being prepared it will switch to the other pipeline. Here
I'm talking specifically of the pentium architecture.
The code inside the while block remains keeps cycling
in the pipeline
until the conditional branch somewhere in between evaluates to true,
which causes a jump to the statement outside the loop. The entire loop
code will have to be unloaded since all of it is a miss. Bigger the
loop, larger the miss (to the extent of the max number of instructions
Yes, you are right here.
Dinesh A. Joshi